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RT8288A Arkusz danych(PDF) 12 Page - Richtek Technology Corporation

Numer części RT8288A
Szczegółowy opis  4A, 21V 500kHz Synchronous Step-Down Converter
PDF  14 Pages
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Producent  RICHTEK [Richtek Technology Corporation]
Strona internetowa  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT8288A Arkusz danych(HTML) 12 Page - Richtek Technology Corporation

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RT8288A
12
DS8288A-03
June 2012
www.richtek.com
©
Copyright
2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Figure 5. Reference Circuit with Snubber and Enable Timing Control
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX)
− TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and
θJAis the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125
°C. The junction to
ambient thermal resistance,
θJA, is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance,
θJA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at TA
= 25
°C can be calculated by the following formula :
PD(MAX) = (125
°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance,
θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the IC.
Keep the traces of the main current paths as short and
wide as possible.
Put the input capacitor as close as possible to the device
pins (VIN and GND).
SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pickup.
Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the IC.
Figure 6. Derating Curve of Maximum Power Dissipation
VIN
VCC
BOOT
FB
SW
6
1
2, 3
4
L
R1
R2
VOUT
VIN
RT8288A
7
CBOOT
COUT
CIN
RT
GND
8, 9 (Exposed Pad)
EN
CC
5
CS*
RS*
REN*
CEN*
* : Optional
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
25
50
75
100
125
Ambient Temperature (°C)
Four-Layer PCB



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