REV. 0

AD5544/AD5554

–7–

Table II. AD5554 Control-Logic Truth Table

CS

CLK

LDAC

RS

MSB

Serial Shift Register Function

Input Register Function

DAC Register

H

X

H

H

X

No Effect

Latched

Latched

L

L

H

H

X

No Effect

Latched

Latched

L

↑+

H

H

X

Shift-Register-Data Advanced One Bit

Latched

Latched

L

H

H

H

X

No Effect

Latched

Latched

↑+

L

H

H

X

No Effect

Selected DAC Updated

Latched

with Current SR Contents

H

X

L

H

X

No Effect

Latched

Transparent

H

X

H

H

X

No Effect

Latched

Latched

HX

↑+

H

X

No Effect

Latched

Latched

H

X

H

L

0

No Effect

H

X

H

L

H

No Effect

NOTES

1. SR = Shift Register.

2.

↑+ positive logic transition; X = Don’t Care.

3. At power ON both the Input Register and the DAC Register are loaded with all zeros.

4. For AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.

5. For AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.

Table III. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB

LSB

Bit Position B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1 B0

Data Word A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1 D0

NOTE

Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the

CS line’s positive edge returns to logic high. At this point an inter-

nally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any

extra bits clocked into the AD5544 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the

LDAC pin can be tied

logic low to disable the DAC Registers.

Table IV. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB

LSB

Bit Position B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Data Word

A1

A0

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NOTE

Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the

CS line’s positive edge returns to logic high. At this point an inter-

nally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any

extra bits clocked into the AD5554 shift register are ignored, only the last 16 bits clocked in are used. If double-buffered data is not needed, the

LDAC pin can be tied

logic low to disable the DAC Registers.

Table V. Address Decode

A1

A0

DAC Decoded

0

0

DAC A

0

1

DAC B

1

0

DAC C

1

1

DAC D