MSC8126_V15 datasheet(21/48 Pages) FREESCALE

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Electrical Characteristics

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

2.5.4.3

Reset Timing Tables

Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or

through the system bus.

Table 12. Timing for a Reset Configuration Write through the DSI or System Bus

No.

Characteristics

Expression

Min

Max

Unit

Required external PORESET duration minimum

•

CLKIN = 20 MHz

•

CLKIN = 133 MHz (400 MHz core)

•

CLKIN = 166 MHz (500 MHz core)

16/CLKIN

800

120

800

—

Delay from deassertion of external PORESET to deassertion of internal

PORESET

•

CLKIN = 20 MHz to 166 MHz

1024/CLKIN

6.17

51.2

µs

Delay from de-assertion of internal PORESET to SPLL lock

•

CLKIN = 20 MHz (RDF = 1)

•

CLKIN = 133 MHz (RDF = 2) (400 MHz core)

•

CLKIN = 166 MHz (RDF = 2) (500 MHz core)

6400/(CLKIN/RDF)

(PLL reference

clock-division factor)

320

µs

Delay from SPLL to HRESET deassertion

•

REFCLK = 40 MHz to 166 MHz

512/REFCLK

3.08

12.8

µs

Delay from SPLL lock to SRESET deassertion

•

REFCLK = 40 MHz to 166 MHz

515/REFCLK

3.10

12.88

µs

Setup time from assertion of

RSTCONF, CNFGS, DSISYNC, DSI64,

CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of

PORESET

3—

Hold time from deassertion of PORESET to deassertion of

RSTCONF,

CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and

MODCK[1–2]

5—

Note:

Timings are not tested, but are guaranteed by design.

Figure 9. Timing Diagram for a Reset Configuration Write

PORESET

Internal

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

RSTCONF, CNFGS, DSISYNC, DSI64

CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]

Host programs

Word

SPLL is locked

(no external indication)

PORESET

Reset Configuration

pins are sampled

MODCK[3–5]

1 + 2

SPLL

locking period

Reset configuration write

sequence during this

period.

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