SSM2005

–10–

REV. 0

D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

DATA

0

1

0

1

0

CLK

DATA

CLK

1

WRITE & LOAD

WRITE & LOAD

1

0

Figure 7. Logic Timing Diagram

Table IV. Timing Description

Timing Symbol

Description

Min

Typ

Max

Units

Input Clock Pulsewidth

50

ns

Input Clock Pulsewidth

50

ns

Data Setup Time

25

ns

Data Hold Time

35

ns

Positive CLK Edge to End of Write

25

ns

Write to Clock Setup Time

35

ns

End of Load Pulse to Next Write (4-Wire Mode)

20

ns

End of Write to Start of Load (4-Wire Mode)

20

ns

Load Pulsewidth (4-Wire Mode)

250

ns

Load Pulsewidth (3-Wire Mode)

250

ns

NOTES:

1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the positive edge.

2. For SPI

LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic

internal

LD signal.)

4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain levels. Refer to the Address/Data Decoding Truth Table.

5. Data must be sent MSB first.

SPI is a trademark of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.