P28/29

Rev. M, May 2010

ML5012

8-2. General procedure of using comparison mode

This procedure below is to compare the analog voltage from the analog voltage between CHA2 and

AGND in single end input mode at PGA Gain = 20.48dB with internal reference digital value at A/D output

range from 0 to 4,095, and VREF = AGND

Operation

Setting

1

Start-up oscillator

ENOSC = 1

2

Set A/D Output Range : 0 to 4,095

AD_Range = 0

3

Set VREF = AGND

VGND = 1

3

Select single end analog input CHA2 and AGND

CHAB_SEL[2:0] = ‘001’ and

CHB_SEL[2:0] = ‘100’

4

Set PGA Gain = 20.48 dB

PGA_Gain Register = ‘1000 0000’

5

Store 12 bits of comparison data at A/D register

A/D[11:0] = ‘XXXX XXXX XXXX’

6

Specify operation mode and start A/D converter

A/D Configuration Register =’1011’

This procedure starts the A/D converter. When the conversion time has elapsed, the converter stops and

stores the result of comparison into bit RSLT of A/D configuration register as follow:

RSLT = ‘1’ when the analog input is higher than the reference voltage

RSLT = ‘0’ when the analog input is lower than the reference voltage