P15/29

Rev. M, May 2010

ML5012

1-6

RR_PGA_AC Command. Read data from A/D Configuration Register

The following diagram shows the timing diagram of read data from A/D Configuration Register.

The DIN data in C1~C4 cycle is RR_AC command code.

The DIN data in C5 cycle is A/D converter enable bit, D11 = EN.

The DIN data in C6 cycle is Storage of comparison result bit, D10 = RSLT.

The DIN data in C7 cycle is Start/Stop bit of A/D converter, D9 = S/S.

The DIN data in C8 cycle is Operation Mode bit of A/D converter, D8 = MD.

The DIN data in C9~C16 cycles are PGA gain setting, D[7:0] = PGA[7:0].

A/D Converter Configuration Register Table

Control

Function

D11

D10

D9

D8

Operations

0

A/D Converter Disable

A/D Converter Enable

(EN)

1

A/D Converter Enable

0

Input voltage * PGA Gain < internal reference voltage

Storage of comparison result

(RSLT)

1

Input voltage * PGA Gain > internal reference voltage

0

Stop A/D Conversion or comparison operation

Start/Stop of A/D Converter

(S/S)

1

Start A/D Conversion or comparison operation

0

A/D Conversion Mode

Operation Mode of A/D Converter

(MD)

1

Comparison Mode