OR3LP26B datasheet(30/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Table 10. Bit Definitions on FPGA/PCI Core Interface

* Command Codes (codes correspond to PCI bus command codes):

0000 Not Used (interrupt acknowledge not implemented)

0001 Not Used (special cycle not implemented)

0010 I/O Read

0011 I/O Write

0100 Reserved (per PCI specification)

0101 Reserved (per PCI specification)

0110 Memory Read

0111 Memory Write

1000 Reserved (per PCI specification)

1001 Reserved (per PCI specification)

1010 Configuration Read

1011 Configuration Write

1100 Memory Read Multiple

1101 Not Used (dual address operation is indicated via separate signal)

1110 Memory Read Line

1111 Memory Write and Invalidate

Bits

Name

Description

A. Dual-Port Master Write, Command and Address

mstatecntr = 0

datafmfpgax[7:3]

—

Unused

datafmfpgax[2]

Dual address indicator (active-high)

datafmfpgax[1:0]

—

Unused

datafmfpga[63:32]

A3 & A2

Address words 3 and 2 (if DA = 1; else must set

all bits to 0s)

datafmfpga[31:0]

A1 & A0

Address words 1 and 0

mcmd[3:0]

mcmd

Master command opcode*

B. Dual-Port Master Write, Data

mstatecntr = 4

datafmfpgax[7:0]

BE7—BE0

Byte enables (active-low)

datafmfpga[63:0]

D7—D0

Data bytes 7 to 0

C. Dual-Port Master Read (Burst Length Cycle)

mstatecntr = 0

datafmfpgax[7:3]

—

Unused

datafmfpgax[2]

Dual address indicator (active-high)

datafmfpgax[1:0]

—

Unused

datafmfpga[63:56]

mrd_benn

Byte enables (active-low)

datafmfpga[55:50]

—

Unused

datafmfpga[49:32]

Burst length (in Quadwords)

datafmfpga[31:0]

A1 & A0

Address words 1 and 0 (set to all 0s if 64-bit

address required—A1 & A0 supplied in next

cycle)

mcmd[3:0]

mcmd

Master command opcode*

D. Dual-Port Master Read (64-Bit Address Cycle)

mstatecntr = 1

datafmfpgax[7:0]

—

Unused

datafmfpga[63:32]

A3 & A2

Address words 3 and 2

datafmfpga[31:0]

A1 & A0

Address words 1 and 0

mcmd[3:0]

—

Unused

E. Dual-Port Master Read, Data

mstatecntr = 4

datatofpgax[7:0]

—

Unused

datatofpga[63:0]

D7—D0

Data bytes 7 to 0

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