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OR3LP26B Arkusz danych(PDF) 67 Page - Agere Systems

Numer części OR3LP26B
Szczegółowy opis  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
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OR3LP26B Arkusz danych(HTML) 67 Page - Agere Systems

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Lucent Technologies Inc.
67
Data Sheet
ORCA OR3LP26B FPSC
March 2000
Embedded Master/Target PCI Interface
Lucent Technologies Inc.
PCI Bus Core Detailed Description Dual Port (continued)
Target Read Memory Burst, Delayed Transaction
Figure 22 (PCI bus) and Figure 23 (FPGA bus) show the timing for a Target memory burst read of four Quadwords
handled as a delayed transaction. The FPGA application indicates its desire to do this by asserting signal deltrn.
On the PCI interface (Figure 22), three transactions are shown. In the first, the PCI core responds to the request
after determining that the address matches one of its BARs by asserting devseln. However, since delayed transac-
tion has been specified by the FPGA application by asserting signal deltrn, the PCI core issues a retry. The PCI
core now waits for the FPGA application to load the Target read FIFO; until this occurs, all memory and I/O
accesses result in retries as exemplified by the second transaction in Figure 22. After the required data is loaded
(either the first data word or a complete FIFO contents, depending on whether the Target read PCI bus hold signal
trpcihold is deasserted or asserted, respectively), the actual data transfer will occur as shown in the third transac-
tion in Figure 22. The FPGA interface timing is as shown in Figure 23. This is similar to the timing for a Target non-
burst read as shown in Figure 20 except that multiple data cycles are required as long as trlastcycn is inactive-
high.
5-8862fF).a
Figure 22. Target Memory Read 32-Byte Burst, Delayed (PCI Bus, 64-Bit)
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9
X
ADRS
X
X ADRS
X
X ADRS
X
D0
D1
D2
D3
X
CMD
BE0
X
X CMD
BE0
X
X CMD
BE0
BE1 BE2 BE3
X
clk
framen
ad
c_ben
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
DELAYED READ REQUEST.
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: NORMAL COMPLETION
BECAUSE READ OPERATION COMPLETED.



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