PCAL9554B datasheet(7/42 Pages) NXP

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PCAL9554B_PCAL9554C

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Product data sheet

Rev. 2 — 10 December 2012

7 of 42

NXP Semiconductors

PCAL9554B; PCAL9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

6.4.3 Polarity inversion register (02h)

The Polarity inversion register (register 2) allows polarity inversion of pins defined as

inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the

corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a

‘0’), the corresponding port pin’s original polarity is retained.

6.4.4 Configuration register (03h)

The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this

bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

6.4.5 Output drive strength registers (40h, 41h)

The Output drive strength registers control the output drive level of the GPIO. Each GPIO

can be configured independently to a certain output current level by two register control

bits. For example, Port 7 is controlled by register 41 CC7 (bits [7:6]), Port 6 is controlled

by register 41 CC6 (bits [5:4]). The output drive level of the GPIO is programmed

00b = 0.25

, 01b = 0.5, 10b = 0.75 or 11b = 1 of the drive capability of the I/O.

See Section 8.2 “Output drive strength control” for more details.

Table 7.

Output port register (address 01h)

Bit

Symbol

Default

Table 8.

Polarity inversion register (address 02h)

Bit

Symbol

Default

Table 9.

Configuration register (address 03h)

Bit

Symbol

Default

Table 10.

Current control register (address 40h)

Bit

Symbol

CC3

CC2

CC1

CC0

Default

Table 11.

Current control register (address 41h)

Bit

Symbol

CC7

CC6

CC5

CC4

Default

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