PCAL9554B datasheet(8/42 Pages) NXP

8 / 42 page

PCAL9554B_PCAL9554C

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Product data sheet

Rev. 2 — 10 December 2012

8 of 42

NXP Semiconductors

PCAL9554B; PCAL9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

6.4.6 Input latch register (42h)

The Input latch register enables and disables the input latch of the I/O pins. These

registers are effective only when the pin is configured as an input port. When an input

latch register bit is 0, the corresponding input pin state is not latched. A state change in

the corresponding input pin generates an interrupt. A read of the input port register clears

the interrupt. If the input goes back to its initial logic state before the input port register is

read, then the interrupt is cleared.

When an input latch register bit is 1, the corresponding input pin state is latched. A change

of state of the input generates an interrupt and the input logic value is loaded into the

corresponding bit of the input port register (registers 0). A read of the input port register

clears the interrupt. If the input pin returns to its initial logic state before the input port

P4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port

read is performed on the input port register, the interrupt is cleared, assuming there were

no additional input(s) that have changed, and bit 4 of the input port register will read ‘1’.

The next read of the input port register bit 4 should now read ‘0’.

An interrupt remains active when a non-latched input simultaneously switches state with a

latched input and then returns to its original state. A read of the input port register reflects

only the change of state of the latched input and also clears the interrupt. The interrupt is

not cleared if the input latch register changes from latched to non-latched configuration.

If the input pin is changed from latched to non-latched input, a read from the input port

latched input, the read from the input port register reflects the latched logic level.

6.4.7 Pull-up/pull-down enable register (43h)

This register allows the user to enable or disable pull-up/pull-down resistors on the I/O

pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting

the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the

resistors will be disconnected when the outputs are configured as open-drain outputs (see

Section 6.4.11). Use the pull-up/pull-down registers to select either a pull-up or pull-down

resistor.

The default value enables pull-up resistors on all I/O pins to match with the non-Agile I/O

devices PCA9554B and PCA9554C.

Table 12.

Input latch register (address 42h)

Bit

Symbol

Default

Table 13.

Pull-up/pull-down enable register (address 43h)

Bit

Symbol

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Default

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