74F381SC datasheet(2/8 Pages) FAIRCHILD

2 / 8 page

www.fairchildsemi.com

Unit Loading/Fan Out

Functional Description

Signals applied to the Select inputs S0–S2 determine the

mode of operation, as indicated in the Function Select

Table. An extensive listing of input and output levels is

shown in the Truth Table. The circuit performs the arith-

metic functions for either active HIGH or active LOW oper-

ands, with output levels in the same convention. In the

Subtract operating modes, it is necessary to force a carry

(HIGH for active HIGH operands, LOW for active LOW

operands) into the Cn input of the least significant package.

The Carry Generate (G) and Carry Propagate (P) outputs

supply input signals to the 74F182 carry lookahead gener-

ator for expansion to longer word length, as shown in Fig-

ure 2. Note that an 74F382 ALU is used for the most

significant package. Typical delays for Figure 2 are given in

Figure 1.

Function Select Table

= HIGH Voltage Level

= LOW Voltage Level

FIGURE 1. 16-Bit Delay Tabulation

FIGURE 2. 16-Bit Lookahead Carry ALU Expansion

Pin Names

Description

U.L.

Input IIH/IIL

HIGH/LOW

Output IOH/IOL

A0–A3

A Operand Inputs

1.0/3.0

µA/−1.8 mA

B0–B3

B Operand Inputs

1.0/3.0

µA/−1.8 mA

S0–S2

Function Select Inputs

1.0/1.0

µA/−0.6 mA

Carry Input

1.0/4.0

µA/−2.4 mA

Carry Generate Output (Active LOW)

50/33.3

−1 mA/20 mA

Carry Propagate Output (Active LOW)

50/33.3

−1 mA/20 mA

F0–F3

Function Outputs

50/33.3

−1 mA/20 mA

Select

Operation

LLL

Clear

B Minus A

A Minus B

A Plus B

⊕B

+ B

HHH

Preset

Path Segment

Toward

Output

Cn + 4, OVR

Ai or Bi to P

7.2 ns

Pi to Cn + ('F182)

6.2 ns

Cn to F

8.1 ns

—

Cn or Cn + 4, OVR

—

8.0 ns

Total Delay

21.5 ns

21.4 ns

74F381SC Arkusz danych(PDF) 2 Page - Fairchild Semiconductor

74F381SC Arkusz danych(HTML) 2 Page - Fairchild Semiconductor

Html Pages

1 2 3 4 5 6 7 8

Arkusz danych Pobierz

Link URL