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MPC823 Arkusz danych(PDF) 51 Page - Freescale Semiconductor, Inc |
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MPC823 Arkusz danych(HTML) 51 Page - Freescale Semiconductor, Inc |
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51 / 70 page ![]() MPC823 ELECTRICAL SPECIFICATIONS 51 Table 14. Serial Communication Controller in NMSI Internal Timing NUM CHARACTERISTIC 25MHZ 40MHZ 50MHZ UNIT MIN MAX MIN MAX MIN MAX 100 RCLK1 and TCLK1 frequency1 0 8.3 0 13 0 16 MHz 102 RCLK1 and TCLK1 rise and all times ÑÑÑÑÑÑ ns 103 TXD2 active delay (from TCLK1 falling edge) 030030030 ns 104 RTS1 active/inactive delay (from TCLK1 falling edge) 030030030 ns 105 CTS1 setup time to TCLK1 rising edge 40 Ñ 40 Ñ 40 Ñ ns 106 RXD2 setup time to RCLK1 rising edge 40 Ñ 40 Ñ 40 Ñ ns 107 RXD2 hold time from RCLK1 rising edge2 0Ñ0Ñ0Ñ ns 108 CD1 setup time to RCLK1 rising edge 40 Ñ 40 Ñ 40 Ñ ns NOTES: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1. 2. Applies to CD and CTS hold time when they are used as external sync signals. Figure 46. SCC NMSI Receive Timing Diagram RCLK1 RXD2 (INPUT) CD1 (INPUT) CD1 (SYNC INPUT) 102 102 101 100 107 106 108 107 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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