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Zakładka z wyszukiwarką danych komponentów |
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MPC823 Arkusz danych(PDF) 62 Page - Freescale Semiconductor, Inc |
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MPC823 Arkusz danych(HTML) 62 Page - Freescale Semiconductor, Inc |
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62 / 70 page  MPC823 ELECTRICAL SPECIFICATIONS Table 18. I2C TimingÑSCL < 100 kHz NUM CHARACTERISTIC 25MHZ 40MHZ 50MHZ UNIT MIN MAX MIN MAX MIN MAX 200 SCL clock frequency (slave) 0 100 0 100 0 100 kHz 200 SCL clock frequency (master) 1.5 100 1.5 100 1.5 100 kHz 202 Bus free time between transmissions 4.7 Ñ 4.7 Ñ 4.7 Ñ ms 203 Low period of SCL 4.7 Ñ 4.7 Ñ 4.7 Ñ ms 204 High period of SCL 4.0 Ñ 4.0 Ñ 4.0 Ñ ms 205 Start condition setup time 4.7 Ñ 4.7 Ñ 4.7 Ñ ms 206 Start condition hold time 4.0 Ñ 4.0 Ñ 4.0 Ñ ms 207 Data hold time 0Ñ0Ñ0Ñ ms 208 Data setup time 250 Ñ 250 Ñ 250 Ñ ns 209 SDL/SCL rise time Ñ1Ñ1Ñ1 ms 210 SDL/SCL fall time Ñ 300 Ñ 300 Ñ 300 ns 211 STOP condition setup time 4.7 Ñ 4.7 Ñ 4.7 Ñ ms NOTE: SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) * pre_scaler * 2 ). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater than or equal to 4/1. Table 19. I2C TimingÑSCL > 100 kHz NUM CHARACTERISTIC MINIMUM MAXIMUM UNIT 200 SCL clock frequency (slave) 0 BRGCLK/48 Hz 200 SCL clock frequency (master) BRGCLK/16512 BRGCLK/48 Hz 202 Bus free time between transmissions 1/(2.2 * fSCL) Ñ sec 203 Low period of SCL 1/(2.2 * fSCL) Ñ sec 204 High period of SCL 1/(2.2 * fSCL) Ñ sec 205 Start condition setup time 1/(2.2 * fSCL) Ñ sec 206 Start condition hold time 1/(2.2 * fSCL) Ñ sec 207 Data hold time 0 Ñ sec 208 Data setup time 1/(40 * fSCL) Ñ sec 209 SDL/SCL rise time Ñ 1/(10 * fSCL) sec 210 SDL/SCL fall time Ñ 1/(33 * fSCL) sec 211 Stop condition setup time 1/(2.2 * fSCL) Ñ sec Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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