STM32L151VBT6DTR datasheet(83/121 Pages) STMICROELECTRONICS

83 / 121 page

STM32L151x6/8/B, STM32L152x6/8/B

Electrical characteristics

Doc ID 17659 Rev 8

83/121

Figure 19.

Recommended NRST pin protection

The reset network protects the device against parasitic resets.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 45. Otherwise the reset will not be taken into account by the device.

6.3.14

TIM timer characteristics

The parameters given in the following table are guaranteed by design.

Refer to Section 6.3.11: I/O current injection characteristics for details on the input/output

alternate function characteristics (output compare, input capture, external clock, PWM

output).

ai17854

STM32L15xxx

RPU

NRST(2)

VDD

Filter

Internal reset

0.1 μF

External

reset circuit(1)

Table 46.

TIMx(1) characteristics

TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

Timer resolution time

tTIMxCLK

fTIMxCLK = 32 MHz

31.25

fEXT

Timer external clock

frequency on CH1 to CH4

fTIMxCLK/2

MHz

fTIMxCLK = 32 MHz

MHz

ResTIM

Timer resolution

bit

tCOUNTER

16-bit counter clock period

when internal clock is

selected (timer’s prescaler

disabled)

65536

tTIMxCLK

fTIMxCLK = 32 MHz 0.0312

2048

µs

tMAX_COUNT Maximum possible count

65536 × 65536

tTIMxCLK

fTIMxCLK = 32 MHz

134.2

STM32L151VBT6DTR Arkusz danych(PDF) 83 Page - STMicroelectronics

STM32L151VBT6DTR Arkusz danych(HTML) 83 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL