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STM8AF6126 Arkusz danych(PDF) 68 Page - STMicroelectronics |
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STM8AF6126 Arkusz danych(HTML) 68 Page - STMicroelectronics |
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68 / 89 page ![]() Electrical characteristics STM8AF61xx, STM8AF62xx 68/89 Doc ID 14952 Rev 6 10.3.10 I2C interface characteristics Table 41. I2C characteristics Symbol Parameter Standard mode I2C Fast mode I2C(1) 1. fMASTER, must be at least 8 MHz to achieve max fast I 2C speed (400 kHz) Unit Min(2) 2. Data based on standard I2C protocol requirement, not tested in production Max(2) Min(2) Max(2) tw(SCLL) SCL clock low time 4.7 - 1.3 - µs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time - 0(4) 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 900(3) tr(SDA) tr(SCL) SDA and SCL rise time (VDD = 3 to 5.5 V) - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time (VDD = 3 to 5.5 V) - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - µs tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - µs tw(STO:STA) STOP to START condition time (bus free) 4.7 - 1.3 - µs Cb Capacitive load for each bus line - 400 - 400 pF |
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