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STM8AF6126 Arkusz danych(PDF) 11 Page - STMicroelectronics |
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STM8AF6126 Arkusz danych(HTML) 11 Page - STMicroelectronics |
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11 / 89 page ![]() STM8AF61xx, STM8AF62xx Block diagram Doc ID 14952 Rev 6 11/89 4 Block diagram Figure 1. STM8A block diagram 1. Legend: ADC: Analog-to-digital converter beCAN: Controller area network BOR: Brownout reset I²C: Inter-integrated circuit multimaster interface IWDG: Independent window watchdog LINUART: Local interconnect network universal asynchronous receiver transmitter POR: Power on reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous asynchronous receiver transmitter Window WDG: Window watchdog XTAL 1 - 16 MHz RC int. 16 MHz RC int. 128 kHz STM8A CORE Debug/SWIM I2C SPI LINUART 16-bit general purpose AWU timer Reset block Reset Clock controller Detector Clock to peripherals and core 10 Mbit/s 16 channels Window WDG IWDG Up to 32 Kbytes Up to 1 Kbytes Up to 2 Kbytes Boot ROM 10-bit ADC 9 CAPCOM Reset 400 Kbit/s Master/slave Single wire automatic debug interf. channels program Flash 16-bit advanced control timer (TIM1) 8-bit basic timer (TIM4) data EEPROM RAM Up to resynchronization timers (TIM2, TIM3) POR BOR |
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