AD1981B

Rev. C | Page 13 of 32

CONTROL REGISTER DETAILS

RESET REGISTER

Index 0x00

Reg No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x00

Reset

X

SE4

SE3

SE2

SE1

SE0

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

0x0090

X is a wild card and has no effect on the value.

Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration).

Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.

SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are 0s).

ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the functions listed in Table 9.

Table 9. ID Bits

Bit

Function

AD1981B

ID0

Dedicated MIC PCM in Channel

0

ID1

Modem Line Codec Support

0

ID2

Bass and Treble Control

0

ID3

Simulated Stereo (Mono to Stereo)

0

ID4

Headphone Out Support

1

ID5

Loudness (Bass Boost) Support

0

ID6

18-Bit DAC Resolution

0

ID7

20-Bit DAC Resolution

1

ID8

18-Bit ADC Resolution

0

ID9

20-Bit ADC Resolution

0

MASTER VOLUME REGISTER

Index 0x02

This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits,

generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility

whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback,

all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.

Reg No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x02

Master

Volume

MM

X

X

LMV4

LMV3

LMV2

LMV1

LMV0

RM1

X

X

RMV4

RMV3

RMV2

RMV1

RMV0

0x8000

If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved.

Table 10.

Bit

Mnemonic

Function

RMV [4:0]

Right Master Volume

Control

The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum

attenuation of 46.5 dB.

RM

Right-Channel Mute

Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the

MM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.

LMV [4:0]

Left Master Volume

Control

The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum

attenuation of 46.5 dB.

MM

Master Volume Mute

When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in

Register 0x76 is set to 1, in which case this mute bit affects only the left channel.