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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AM3703CUS Arkusz danych(PDF) 94 Page - Texas Instruments |
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AM3703CUS Arkusz danych(HTML) 94 Page - Texas Instruments |
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94 / 280 page  AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com Table 2-5. External Memory Interfaces – GPMC Signals Description(1) (continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM [1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] BOTTOM PIN (CBP (CBP (CUS MULTIPLEXING Pkg.) [4] Pkg.) [5] Pkg.) [4] [6] gpmc_d10 GPMC data bit 10 / multiplexed IO P1 AB4 T1 N1 U1 gpmc_d10 address gpmc_a11 gpmc_d11 GPMC data bit 11 / multiplexed IO R1 AC4 U2 P2 R3 gpmc_d11 address gpmc_a12 gpmc_d12 GPMC data bit 12 / multiplexed IO R2 AB6 U1 P1 T3 gpmc_d12 address gpmc_a13 gpmc_d13 GPMC data bit 13 / multiplexed IO T2 AC6 P1 M1 U2 gpmc_d13 address gpmc_a14 gpmc_d14 GPMC data bit 14 / multiplexed IO W1 AB7 L2 J2 V1 gpmc_d14 address gpmc_a15 gpmc_d15 GPMC data bit 15 / multiplexed IO Y1 AC7 M2 K2 V2 gpmc_d15 address gpmc_a16 gpmc_ncs0 GPMC Chip Select bit 0 O G4 Y2 AD8 AA8 E2 NA gpmc_ncs1 GPMC Chip Select bit 1 O H3 Y1 AD1 W1 NA NA gpmc_ncs2 GPMC Chip Select bit 2 O V8 NA A3 NA NA NA gpmc_ncs3 GPMC Chip Select bit 3 O U8 NA B6 NA D2 NA gpmc_ncs4 GPMC Chip Select bit 4 O T8 NA B4 NA F4 NA gpmc_ncs5 GPMC Chip Select bit 5 O R8 NA C4 NA G5 NA gpmc_ncs6 GPMC Chip Select bit 6 O P8 NA B5 NA F3 NA gpmc_ncs7 GPMC Chip Select bit 7 O N8 NA C5 NA G4 NA gpmc_io_dir GPMC IO direction control for use O N8 NA C5 NA G4 NA with external transceivers gpmc_clk GPMC clock O T4 W2 N1 L1 W2 NA gpmc_nadv_ale Address Valid or Address Latch O F3 W1 AD10 AA9 F1 NA Enable gpmc_noe Output Enable O G2 V2 N2 L2 F2 NA gpmc_nwe Write Enable O F4 V1 M1 K1 G3 NA gpmc_nbe0_cle Lower Byte Enable. Also used for O G3 AC12 K2 NA K5 NA Command Latch Enable gpmc_nbe1 Upper Byte Enable O U3 NA J1 NA L1 NA gpmc_nwp Flash Write Protect O H1 AB10 AC6 Y5 E1 NA gpmc_wait0 External indication of wait I M8 AB12 AC11 Y10 C1 NA gpmc_wait1 External indication of wait I L8 AC10 AC8 Y8 NA NA gpmc_wait2 External indication of wait I K8 NA B3 NA NA NA gpmc_wait3 External indication of wait I J8 NA C6 NA C2 NA (1) NA in table stands for "Not Applicable". NOTE For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem / SDRC Subsystem Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). 94 TERMINAL DESCRIPTION Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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