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MPC8548ECHXATHA Arkusz danych(PDF) 72 Page - Freescale Semiconductor, Inc |
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MPC8548ECHXATHA Arkusz danych(HTML) 72 Page - Freescale Semiconductor, Inc |
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72 / 151 page ![]() MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9 72 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) 16.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected must provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise occurs in the 1–15 MHz range. The source impedance of the clock driver must be 50 to match the transmission line and reduce reflections which are a source of noise to the system. The detailed AC requirements of the SerDes reference clocks are defined by each interface protocol based on application usage. See the following sections for detailed information: • Section 17.2, “AC Requirements for PCI Express SerDes Clocks” • Section 18.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK” 16.2.4.1 Spread Spectrum Clock SD_REF_CLK/SD_REF_CLK are designed to work with a spread spectrum clock (+0% to –0.5% spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation must be used. 16.3 SerDes Transmitter and Receiver Reference Circuits Figure 47 shows the reference circuits for SerDes data lane’s transmitter and receiver. Figure 47. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express, Serial Rapid IO, or SGMII) in this document based on the application usage: • Section 17, “PCI Express” • Section 18, “Serial RapidIO” Note that external an AC coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in the specification of each protocol section. SD_TXn SD_TXn SD_RXn SD_RXn 50 Receiver Transmitter 50 50 50 |
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