MPC8548ECHXATHA datasheet(16/151 Pages) FREESCALE

16 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Input Clocks

This section discusses the timing for the input clocks.

4.1

System Clock Timing

The following table provides the system clock (SYSCLK) AC timing specifications for the device.

4.2

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then

used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter

specification. The minimum pulse width of the RTC signal must be greater than 2x the period of the CCB

clock. That is, minimum clock high time is 2

 t

CCB, and minimum clock low time is 2  tCCB. There is

no minimum RTC frequency; RTC may be grounded if not needed.

Table 5. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

—

133

MHz

1, 6, 7, 8

SYSCLK cycle time

tSYSCLK

7.5

—

6, 7, 8

SYSCLK rise and fall time

tKH, tKL

0.6

1.0

1.2

SYSCLK duty cycle

tKHK/tSYSCLK

—

SYSCLK jitter

—

±150

4, 5

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies.See Section 20.2, “CCB/SYSCLK PLL Ratio,” and Section 20.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth must be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.

7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on

SYSCLK.

8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum.

MPC8548ECHXATHA Arkusz danych(PDF) 16 Page - Freescale Semiconductor, Inc

MPC8548ECHXATHA Arkusz danych(HTML) 16 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL