PTH12050LAH datasheet(3/26 Pages) TI1

3 / 26 page

www.ti.com

ELECTRICAL CHARACTERISTICS

PTH12050W/L

SLTS214H – MAY 2003 – REVISED OCTOBER 2007

TA = 25°C; VI = 12 V; VO = 3.3 V; C1 = 100 µF, C2 = 10 µF, C3 = 0 µF, and IO = IO(max) (unless otherwise stated)

PARAMETER

TEST CONDITIONS

PTH12050W

UNIT

MIN

TYP

MAX

°C, 400 LFM airflow

(1)

Output current

Over

ΔVadj range

°C, natural convection

(1)

Input voltage range

Over IO range

10.8

13.2

Vo tol

Set-point voltage tolerance

±2

(2)

%Vo

ΔRegtemp

Temperature variation

–40

°C <T

A < 85°C

±0.5

%Vo

ΔRegline

Line regulation

Over VI range

±5

ΔRegload

Load regulation

Over IO range

±5

ΔRegtot

Total output variation

Includes set-point, line, load, –40

°C ≤ T

A ≤ 85°C

±3

(2)

%Vo

ΔVadj

Output voltage adjust range

Over VI range

1.2

5.5

(1)

RSET = 280 Ω, VO = 5 V

(1)

93%

RSET = 2 kΩ, VO = 3.3 V

(1)

91%

RSET = 4.32 kΩ, VO = 2.5 V

89%

Efficiency

IO = 5 A

RSET = 8.06 kΩ, VO = 2 V

88%

RSET = 11.5 kΩ, VO = 1.8 V

87%

RSET = 24.3 kΩ, VO = 1.5 V

86%

RSET = open circuit, VO = 1.2 V

84%

VO ≤ 2.5 V

mVpp

VO ripple (peak-to-peak)

20-MHz bandwidth

VO > 2.5 V

%Vo

Iotrip

Overcurrent threshold

Reset, followed by auto-recovery

ttr

1 A/µs load step,

Recovery time

µs

Transient response

50 to 100% IOmax,

ΔVtr

VO over/undershoot

100

C3 = 100 µF

IIL track

Track input current (pin 2)

Pin to GND

–0.13

(3)

dVtrack/dt

Track slew rate capability

CO ≤ CO(max)

V/ms

VI increasing

9.5

10.4

UVLO

Under-voltage lockout

VI decreasing

8.8

VIH

Input high voltage, Referenced to GND

Open

(3)

VIL

Inhibit Control (pin 4)

Input low voltage, Referenced to GND

–0.2

0.5

IIL

Input low current, Pin 4 to GND

0.24

Input standby current

Inhibit (pin 4) to GND, Track (pin 2) open

f s

Switching frequency

Over VI and IO ranges

260

320

380

kHz

External input capacitance, C1

100

(4)

µF

Nonceramic

100

(5)

3300

(6)

Capacitance value

µF

External output capacitance, C3

Ceramic

300

Equivalent series resistance (nonceramic)

(7)

5.9

MTBF

Reliability

Per Bellcore TR-332 50% stress, TA = 40°C, ground benign

6 Hr

(1)

See the Temperature Derating (SOA) curves in the Typical Characteristics section for appropriate derating.

(2)

The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a

tolerance of 1% with 100 ppm/

°C or better temperature stability.

(3)

This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 2). If it is left open-circuit, the module operates when input

power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do

not place an external pull-up on this pin. For further information, see the related application note.

(4)

A 100 µF electrolytic input capacitor is required for proper operation. The electrolytic capacitor must be rated for a minimum of 750 mA

rms of ripple current. An additional 10 µF ceramic capacitor is required for output voltages 3.3 V and higher. For further information, see

the related application information on capacitor selection.

(5)

An external output capacitor is not required for basic operation. Adding 100 µF of distributed capacitance at the load improves the

transient response.

(6)

This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a

voltage supervisor, CO(max) is reduced to 2200 μF. See the application notes for further guidance.

(7)

This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m

Ω as the minimum when using max-ESR values

to calculate.

Submit Documentation Feedback

Product Folder Link(s): PTH12050W/L

PTH12050LAH Arkusz danych(PDF) 3 Page - Texas Instruments

PTH12050LAH Arkusz danych(HTML) 3 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Arkusz danych Pobierz

Link URL