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AM79C873KCW Arkusz danych(PDF) 13 Page - Advanced Micro Devices

Numer części AM79C873KCW
Szczegółowy opis  NetPHY??-1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
PDF  44 Pages
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Producent  AMD [Advanced Micro Devices]
Strona internetowa  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C873KCW Arkusz danych(HTML) 13 Page - Advanced Micro Devices

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Am79C873
13
PRELIMINARY
s RX_DV (receive data valid) input from the PHY to in-
dicate the PHY is presenting recovered and de-
coded nibbles to the MAC reconciliation sublayer. To
interpret a receive frame correctly by the reconcilia-
tion sublayer, RX_DV must encompass the frame
starting no later than the Start-of-Frame delimiter
and excluding any End-Stream delimiter.
s RX_ER (receive error) transitions synchronously
with respect to RX_CLK. RX_ER will be asserted
for 1 or more clock per iods to indicate to
the reconciliation sublayer that an error was
detected somewhere in the frame being transmit-
ted from the PHY to the reconciliation sublayer.
s CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle and
deasserted by the PHY when the transmit and receive
medium are idle. Figure 2 depicts the behavior of CRS
during 10BASE-T and 100BASE-TX transmission.
Figure 2.
Carrier Sense during 10BASE-T and 100BASE-TX Transmission
100BASE Operation
The 100BASE transmitter receives 4-bit nibble data
clocked in at 25 MHz at the MII and outputs a scram-
bled 5-bit encoded MLT-3 signal to the media at 100
Mbps. The on-chip clock circuit converts the 25 MHz
clock into a 125 MHz clock for internal use.
The IEEE 802.3u specification defines the Media Inde-
pendent Interface. The interface specification defines a
dedicated receive data bus and a dedicated transmit
data bus.
These two busses include various controls and signal
indications that facilitate data transfers between the
NetPHY-1 device and the Reconciliation layer.
100BASE Transmit
The 100BASE transmitter consists of the functional
blocks shown in Figure 3. The 100BASE transmit sec-
tion converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125 million symbols per sec-
ond serial data stream.
TXD
Preamble
SFD
Data
EFD
Preamble
SFD
Data
ESD
T/R
SSD
J/K
10Base-T
100Base-TX
TXD
CRS
CRS
IDLE
IDLE
22164A-4



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