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AM79C981 Arkusz danych(PDF) 21 Page - Advanced Micro Devices |
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AM79C981 Arkusz danych(HTML) 21 Page - Advanced Micro Devices |
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21 / 40 page ![]() AMD PRELIMINARY 1–91 Am79C981 Am79C981 IMR+ Chip XTAL OSC CK D Q ASYNC RESET X1 X2 RST STR CRS CLR CK Q Q D 1/2 ’74 TCK CK SI SIPO CK Register T P 7 T P 6 T P 5 T P 0 A U I Shift Register Carrier Sense Outputs 1/2 ’74 TCK 17306B-9 Figure 5a. Port Activity Monitor Implementation 17306B-10 RST X1 TCK (Note 1) CRS STR (Note 3) 12 9 10 11 AUI TP0 TP1 TP7 X AUI TP0 (Note 2) Notes: 1. Externally generated signal illustrates internal IMR+ chip clock phase relationship. 2. IMR+ chip standalone, X will be low. When attached to a HIMIB device, X reflects the state of the CI pair. 3. STR signal is not available when the IMR+ chip is attached to HIMIB device, and must be generated externally. Figure 5b. Port Activity Monitor Implementation (Continued) |
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