© 1999 California Micro Devices Corp. All rights reserved.

11/98

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CALIFORNIA MICRO DEVICES

PAC DN017

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

Application Information

See also California Micro Devices Application note AP209, “Design Considerations for ESD protection.”

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse

applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per

Figure 1

Input Capacitance vs. Input Voltage

When placing an order please specify desired shipping: Tubes or Tape & Reel.

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