SERIES 2 FLASH MEMORY CARDS

PRINCIPLES OF DEVICE OPERATION

Individual 28F008SA devices include a Command

User Interface (CUI) and a Write State Machine

(WSM) to manage write and erase functions in each

device block

The CUI serves as the device’s interface to the Card

Control Logic by directing commands to the appro-

priate device circuitry (Table 4) It allows for fixed

power supplies during block erasure and data writes

The CUI handles the WE

interface into the device

data and address latches as well as system soft-

ware requests for status while the WSM is operating

The CUI itself does not occupy an addressable

memory location The CUI provides a latch used to

store the command and address and data informa-

tion needed to execute the command Erase Setup

and Erase Confirm commands require both appropri-

ate command data and an address within the block

to be erased The Data Write Setup command re-

quires both appropriate command data and the ad-

dress of the location to be written while the Data

Write command consists of the data to be written

and the address of the location to be written

The CUI initiates flash memory writing and erasing

the application the system designer may choose to

when writes and erases are required) or hardwired to

curred and memory contents cannot be altered The

CUI architecture provides protection from unwanted

write and erase operations even when high voltage

are enabled The WSM automates the writing and

erasure of blocks within a device This on-chip state

machine controls block erase and data-write freeing

the host processor for other tasks After receiving

the Erase Setup and Erase Confirm commands from

the CUI the WSM controls block-erase Progress is

monitored via the device’s status register the card’s

control logic

and the RDYBSY

pin of the

PCMCIA interface Data-write is similarly controlled

after destination address and expected data are

supplied

Table 4 Device Command Set

Cycles

Req’d

Bus

First Bus Ccyle

Second Bus Cycle

Data

Data

x8 Mode x16 Mode

x8 Mode x16 Mode

Read ArrayReset

1

Write

DA

FFH

FFFFH

Intelligent Identifer

3

Write

DA

90H

9090H

Read

IA

Read Device Status Register

2

Write

DA

70H

7070H

Read

DA

Clear Device Status Register

1

Write

DA

50H

5050H

Erase SetupErase Confirm

2

Write

BA

20H

2020H

Write

BA

D0H

D0D0H

Erase Suspend

2

Write

DA

B0H

B0B0H

Write

DA

D0H

D0D0H

Erase Resume

Write SetupWrite

2

Write

WA

40H

4040H

Write

WA

2

Write

WA

10H

1010H

Write

WA

NOTES

1 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

3 Following the intelligent identifier command two read operations access manufacturer (89H) and device codes (A2H)

6 Either 40H or 10H are recognized by the WSM as the Write Setup command

16