ADMCF341_15 datasheet(24/36 Pages) AD

Numer części	ADMCF341

Szczegółowy opis	28-Lead Flash and ROM Memory, Mixed-Signal DSPs with Enhanced Analog Front End

PDF	36 Pages

Scroll/Zoom	100%

Producent	AD [Analog Devices]

Strona internetowa	http://www.analog.com

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24 / 36 page

REV. A

–24–

ADMC(F)341

DSP

CORE

SPORT1

DT1

FL1

TFS1

RFS1

DR1

SCLK1

DSP

CORE

SPORT0

DT1

FL1

TFS1

RFS1

SCLK1

SPI

CONTROL

BLOCK

MODECTRL REGISTER (04)

SPORT1 BOOT MODE/UART MODE

MODECTRL REGISTER (15)

SPORT0 SPORT MODE/UART MODE

MODECTRL REGISTER (14..13..12)

SPORT0 SPI INTERFACE CONTROL

DT1/FL1

DR1

SCLK1/SCLK0

DT0

DR0

TFS0

RFS0

Figure 19. SPORT0 and SPORT1 Internal Multiplexing (Simplified Diagram)

Table XI. SPORT0 Pin Assignment in SPI Mode

SPORT I/O Signal

SPI Mode

SPI Mode I/O

DT0 (Data Transmit)

MOSI

Output

(Master Output/

Slave Input)

DR0

MISO

Input

(Master Input/

Slave Output)

TFS0

Output

(Slave Select)

RFS0

Unused

N/A

SCLK0

SCK

Output

(Serial Clock)

The slave select pin automatically generates the select signal

at each word transfer. This pin can also be used as a general-

purpose I/O during the SPI transfer without affecting the

SPORT operations.

The SPI clock polarity and phase are configurable through

Bits 13 and 12 of the MODECTRL register. The SPI transfer

using clock phase is shown in Figures 20 and 21.

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