AN4092 datasheet(23/38 Pages) STMICROELECTRONICS

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AN4092

Configuration pins and unused IOs

Doc ID 023080 Rev 2

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Configuration pins and unused IOs

In the SPC564Axx / SPC563Mxx there are many configuration pins, they allow to choose

the boot mode, the clock reference and the weak pull-up/pull-down configuration:

●

BOOTCFG0 (SPC564Axx only), BOOTCFG1

●

PLLREF

●

WKPCFG

●

RSTCFG (SPC564Axx only)

For legacy reasons, PLLCFG1 is still described in the documentation but there is no

configuration functionality assigned to this pin any longer.

After the reset those pins can be used as GPIO or any of the other functions available.

3.1

Boot modes (SPC564Axx)

BOOTCFG0 and BOOTCFG1 allow the selection of the boot mode. In the QFP176 package

only BOOTCFG1 is available outside while BOOTCFG0 is pulled low internally.

By default both signals are pulled down after reset. If needed, BOOTCFG pins must be

pulled high to VDDEH6. The reset controller latches the value on the BOOCFG[0:1] input to

the SIU_RSR (Reset Status Register) four clock cycles prior to the negation of RSTOUT.

The BAM reads the BOOTCFG status from the SIU_RSR and acts accordingly.

Boot from external bus interface is obviously possible only on the BGA324 package.

3.2

Boot modes (SPC563Mxx)

BOOTCFG1 allows the selection of the boot mode:

■

BOOTCFG = 0, internal boot (form FLASH)

■

BOOTCFG = 1, serial boot (eSCI / FlexCAN)

BOOTCFG1 is pulled down after reset by default.

3.3

Clock reference

As described in the section Section 2.2: Crystal or external reference, the PLLREF pin

determines the source of the reference clock, either crystal or external at the negation of the

/RSTOUT. During assertion of the /RSTOUT, the system clock switches to the input

Table 5.

Boot modes

BOOTCFG[0:1]

Boot Mode Name

Internal boot (from FLASH)

Serial boot (eSCI / FlexCAN)

External boot

Reserved

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