AN487 APPLICATION NOTE

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Figure 20. Bode plot of the regulation loop with the compensation network of fig. 19.

The criterium is to define Z1, Z2 close to the resonant pole of the output LC filter. The Gm/2PC1 pole must

be placed at a frequency at which open loop gain is below 0 dB axis (Fig. 20).

CURRENT LIMITATION

Current limitation is implemented intrnally to the chip and doesn’t need any external component.

The output current is sensed by an internal resistor in series with the drain of the power transistor. On chip

trimming guarantees +10% accuracy on the value of peak current limitation.

Current limit protection works pulse by pulse with lowering of tnhe switching frequency. Fig.21 shows cir-

cuital implementation of current protection.

Figure 21. Current protection circuit.