AN3063 datasheet(4/33 Pages) STMICROELECTRONICS

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Main characteristics and circuit description

AN3063

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Doc ID 16261 Rev 3

Main characteristics and circuit description

The main characteristics of the SMPS are listed below:

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Line voltage range: 90 to 265 Vac

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Minimum line frequency (fL): 47 Hz

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Regulated output voltage: 400 V

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Rated output power: 100 W

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Maximum 2fL output voltage ripple: 20 V pk-pk

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Hold-up time: 10 ms (VDROP after hold-up time: 300 V)

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Minimum switching frequency: 40 kHz

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Minimum estimated efficiency: 92% (at Vin = 90 Vac, Pout = 100 W)

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Maximum ambient temperature: 50°C

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PCB type and size: single side, 35 µm, CEM-1, 90 x 83 mm

This demonstration board implements a power factor correction (PFC) pre-regulator, 100 W

continuous power, on a regulated 400 V rail from a wide-range mains voltage and provides

for the reduction of the mains harmonics, allowing to meet the European EN61000-3-2 or

the Japanese JEITA-MITI standard. The regulated output voltage is typically the input for the

cascaded isolated DC-DC converter thatprovides the output rails required by the load.

The board is designed to allow full-load operation in still air.

The power stage of the PFC is a conventional boost converter, connected to the output of

the rectifier bridge D1. It is completed by the coil L2, the diode D3 and the capacitor C6. The

boost switch is represented by the power MOSFET Q1. The NTC R1 limits the inrush

current at switch-on. It has been connected on the DC rail, in series to the output electrolytic

capacitor, in order to improve the efficiency during low-line operation because the RMS

current flowing into the output stage is lower than current flowing into the input one at the

same input voltage, thus increasing efficiency. The board is equipped with an input EMI filter

necessary to filter the commutation noise coming from the boost stage.

At startup the L6563H is powered by the electrolytic capacitor C11 that is charged via high-

voltage startup (HVS) pin #9. The HVS pin, able to withstand 700 V, is connected directly to

the rectified mains voltage. A 0.85 mA (typ.) internal current source charges the capacitor

C11 connected between Vcc pin #16 and GND pin #14 until the voltage on the Vcc pin

reaches the startup threshold. The L2 secondary winding and the charge pump circuit (C7,

R4, D4 and D5) generate the Vcc voltage, powering the L6563H during normal operation.

The L2 secondary winding is also connected to the L6563H pin #13 (ZCD) through the

resistor R5. Its purpose is to supply the information that L2 has demagnetized, needed by

the internal logic for triggering a new switching cycle.

The divider R9, R12, R17 and R19 provides the L6563H multiplier with the information of the

instantaneous mains voltage that is used to modulate the peak current of the boost.

The resistors R2, R8, R10 with R13 and R14 are dedicated to sense the output voltage and

feed back to the L6563H the information necessary to regulate the output voltage. The

components C9, R18 and C8 constitute the error amplifier compensation network necessary

to keep the required loop stability.

The peak current is sensed by resistors R25 and R26 in series to the MOSFET and the

signal is fed into pin #4 (CS) of the L6563H via the filter composed of R24 and C15.

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