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PM0222 Arkusz danych(PDF) 7 Page - STMicroelectronics |
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PM0222 Arkusz danych(HTML) 7 Page - STMicroelectronics |
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7 / 33 page ![]() DocID025476 Rev 1 7/33 PM0222 Brain status after boot 33 2 Brain status after boot To summarize, the Flash memory array in Brain is divided in two blocks: The information block: this section is reserved by STMicroelectronics to store manufacturing information and proprietary boot code. The main Flash memory containing the customer program and data. This corresponds to the Flash mentioned throughout this document. When the reset is released, Cortex-M0 starts to execute the STMicroelectronics proprietary code in the Flash information block. Then, this boot code copies the vector table from the main Flash to the RAM bank 1 base address and transfers the execution of the code to the customer’s application. In order to execute this step, the vector table of the customer’s application must be present at the start address of the main Flash as specified in Table 2. The default settings in order for Cortex-M0 to drive the main Flash to execute customer code are indicated in Table 3. Table 2. Customer code inputs to provide Address where customer needs to put information Information to provide 0x1001_0000 - 0x1001_00C0 Vector table(1) 1. See “Interrupt vectors” table in the Brain reference manual, Interrupt chapter and in the “Cortex-M0 Devices Generic User Guide”, §2.3.4 for more details. Table 3. Default device settings after boot Parameter Description Value REMAP Indicates if main Flash or ECC RAM bank 0 seen at address 0x1001_0000 ‘0’ (if main Flash seen at address 0x1001_0000) Clock tree System clock source Processor clock 80 MHz internal RC System clock / 5 = 16 MHz ECC RAM bank 0 Error code correction mechanism ON (but RAM not initialized) |
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