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PWM GENERATION WITH ST62 AUTO-RELOAD TIMER

The length of the loop “adc_loop” is the interval at which the duty cycle of the PWM signal will

be updated. In this example, this loop lasts around 7

6µs, so the PWM duty cycle is updated

every 2 or 3 PWM cycles.

Calculation of the 8

0µs:

- Instructions ldi, ld and jp last 4 cycles of 13 clock periods -> 4 x 4 x 13 8MHz periods =

26µs

- Instruction jrr lasts as long as the A/D takes to do the conversion, which is around 50µs at

8MHz -> total length of adc_loop at 8 MHz = approx. 76µs

This last example shows that, as requested, the CPU is not used to generate the PWM signal,

but only to start/stop it and to update the duty cycle.