Rev 2

1/5

AN592

Application note

June 2008

PLL

generation using ST62 auto-reload timer

Figure 1. Auto-reload Timer Block Diagram

INTRODUCTION

This note describes how to generate a digital signal locked in phase and frequency (PLL) with a

calibrated delay starting from an active edge on the Auto-reload timer input pin.

Auto-reload timer description

This timer is an 8 bit timer/counter with prescaler. It includes auto-reload PWM, capture and

compare capability with one input and one output pins. It can be controlled by the following reg-

isters (8 bit):

It can also wake-up the MCU from wait mode and exit from stop mode if an external event is

present on the input pin. The prescaler ratio can be programmed to choose the timer input fre-

Example:

The TIMIN input receives a 15 kHz digital signal. We want to generate a phase-locked 15 kHz

digital signal with a falling edge delayed 19

μs from the input rising edge, and a duty cycle of

75%. The CPU quartz frequency is 8 MHz.