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AN592 Arkusz danych(PDF) 3 Page - STMicroelectronics

Numer części AN592
Szczegółowy opis  PLL generation using ST62 auto-reload timer
PDF  5 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN592 Arkusz danych(HTML) 3 Page - STMicroelectronics

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PLL Generation using ARTimer
3/5
highest number: 255 (for best resolution). In this case 66.7
μs / 255 = 0.26μs is the smallest TC
clock period that we can use. With a prescaler ratio of 1, the TC clock period is 1/8MHz = 0.125
μs. So we need a prescaler ratio of 3, giving a TC clock period of 3/8 MHz = 0.375μs. This is the
elementary incrementing time of the TC counter, which gives the resolution of the phase shift
and of the low level on TIMOUT (the TC counter is incremented with a clock FIN = 1/0.375
μs=
2667kHz).
The desired delay is 19
μs: CP - RC = 19μs /0.375μs = 50.67.
The TIMIN period is:
TOT = 66.7
μs / 0.375 μs = 177.78.
The duty cycle is: 0.25 = (255 - CP)/TOT
Rounding the decimals, this gives:
RC = 160; CP = 210; TOT = 178
The variable time TVAR is: TVAR =TOT-255+RC=83
The condition is met: Tvar is positive and smaller than CP: (255 - 160) < 178 < (255 - 160 + 210)
The TIMOUT signal will remain correct and stable as long as this condition is met, even if the in-
put frequency varies:
The input frequency limits for output correctness are:
(255 - 160) x 0.375
μs<TIN < (255 - 160 + 210) x 0.375μs
The output signal will remain locked in phase and frequency as long as the input signal TIMIN
is in the range:
8.7kHz < TIMIN frequency < 28kHz
Of course, it is also possible to modify by software the 19
μs delay and the 75% duty cycle, for
example by measuring repetitively an error voltage with the A/D converter and calculating the
modified delay or duty cycle.
;**************** A-R Timer Register Set *******************
RC
.def 0D9h,0FFh,0FFh
;reload/capture register
CP
.def 0DAh,0FFh,0FFh
;compare register
MC
.def 0D5h,0FFh,0FFh
;mode control register
SC0
.def 0D6h,0FFh,0FFh
;status/control register 0
SC1
.def 0D7h,0FFh,0FFh
;status/control register 1
LR
.def 0DBh,0FFh,0FFh
;load register
;============================================================
ldi CP, 210
;compare register = 210d
ldi RC, 160
;reload register = 160d
ldi SC1,00000101b
;clock source= CPU clock divided by 3
;rising TIMIN edge active
;pull-up disabled, prescaler ratio = 1
ldi MC, 11100011b
;load on TIMIN mode,interrupts disabled
;PWMOUT enabled, start timer
Program example



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