AN2260

1 General description

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1

General description

The STR73x is normally woken up in SystemMemory boot Mode when the Flash is still not

programmed in the manufacturing line environment. In this case the system boot is performed

from SystemMemory sector in the Flash bank0. This mode allows initializing the Flash

programming via a serial interface. The SystemMemory code is going to load a Flash

programming code (called “loader” from now on) into internal RAM via the UART0 serial

interface.

1.1

Entering SystemMemory boot mode

The STR73x enters the SystemMemory Boot Mode if the mode pins are configured with M0=0,

M1=1 as the hardware reset pin (RSTIN) transitions High at the end of a hardware reset. The

M1 signal is used to stretch the internal clock. M1 must be forced back to Low (0) after the

RSTIN pin has stabilized. Forcing M1 Low is required in order to enable propagation of the

system clock throughout the device.

As the M1 pin is forced Low the STR73x CPU begins executing the SystemMemory code which

resides in the SystemMemory Sector now mapped at address 0x00000000.

Note:

The normal Flash boot sector will not be available at address 0x00000000 until the

SystemMemory sector is re-mapped to 0x8010C000 by clearing the SMBM bit in the Flash

Control Register 0. The SystemMemory code does not perform this re-mapping operation.

Table 1.

STR73x device configuration in SystemMemory Boot Mode

1.2

Hardware requirements

The hardware required for putting the STR73x into SystemMemory boot mode would consist of

any circuitry, switch, or jumper capable of holding the M1 pin High during Reset, and then

forcing M1 Low after the reset is complete. For more details refer to the application note

STR73x Hardware Getting Started (AN2156), Boot Management section.

To connect to the STR73x during SystemMemory boot mode, a RS232 serial interface must be

directly linked to UART0 pins, for more details refer to the AN2156 document.

Feature/Peripheral

State

Comment

Instruction Set

THUMB

Save code space with 16-bit instructions

CPU Mode

Supervisor

Full access with IRQ/FIQs disabled

Input Clock

External Quartz

allow a Frequency in a range of 4 to 8MHz

CLK2

Div2 Enabled

-

PLL

Free running

MX=12

DX=2

System Clock in a range of 12 to 24MHz to enable

higher serial link baudrates

UART0_RX Pin

Input

UART0 receive

UART0_TX Pin

Default

Only configured for UART Boot

UART0 Registers

Default

Only configured for UART Boot