DocID15687 Rev 5

23/29

PM0059

Flash memory interface

28

2.8.5

Flash control register (FLASH_CR)

The Flash control register is used to configure and start Flash memory operations.

Address offset: 0x10

Reset value: 0x8000 0000

Access: no wait state when no Flash memory operation is ongoing, word, half-word and

byte access.

Bits 3:2 Reserved, must be kept cleared.

Bit 1 OPERR: Operation error

Set by hardware when a flash operation (programming / erase) request is detected and can

not be run because of parallelism, alignment, sequence or write protection error. This bit is

set only if error interrupts are enabled (ERRIE = 1).

Bit 0 EOP: End of operation

Set by hardware when one or more Flash memory operations (program/erase) has/have

completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =

1).

Cleared by writing a 1.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

LOCK

Reserved

ERRIE

EOPIE

Reserved

STRT

rs

rw

rw

rs

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

PSIZE[1:0]

Reserv

ed

SNB[3:0]

MER

SER

PG

rw

rw

rw

rw

rw

rw

rw

rw

rw

Bit 31 LOCK: Lock

Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is

cleared by hardware after detecting the unlock sequence.

In the event of an unsuccessful unlock operation, this bit remains set until the next reset.

Bits 31:26 Reserved, must be kept cleared.

Bit 25 ERRIE: Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is

set to 1.

0: Error interrupt generation disabled

1: Error interrupt generation enabled

Bit 24 EOPIE: End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes

to 1.

0: Interrupt generation disabled

1: Interrupt generation enabled

Bits 23:17 Reserved, must be kept cleared.

Bit 16 STRT: Start

This bit triggers an erase operation when set. It is set only by software and cleared when the

BSY bit is cleared.

Bits 15:10 Reserved, must be kept cleared.