PM0214 datasheet(64/245 Pages) STMICROELECTRONICS

64 / 245 page

The STM32 Cortex-M4 instruction set

PM0214

64/245

DocID022708 Rev 4

3.3.5

Address alignment

An aligned access is an operation where a word-aligned address is used for a word, dual

word, or multiple word access, or where a halfword-aligned address is used for a halfword

access. Byte accesses are always aligned.

The Cortex-M4 processor supports unaligned access only for the following instructions:

•

LDR, LDRT

•

LDRH, LDRHT

•

LDRSH, LDRSHT

•

STR, STRT

•

STRH, STRHT

All other load and store instructions generate a usage fault exception if they perform an

unaligned access, and therefore their accesses must be address aligned. For more

information about usage faults see Fault handling on page 43.

Unaligned accesses are usually slower than aligned accesses. In addition, some memory

regions might not support unaligned accesses. Therefore, ARM recommends that

programmers ensure that accesses are aligned. To avoid accidental generation of unaligned

accesses, use the UNALIGN_TRP bit in the configuration and control register to trap all

unaligned accesses, see Configuration and control register (CCR) on page 215.

3.3.6

PC-relative expressions

A PC-relative expression or label is a symbol that represents the address of an instruction or

literal data. It is represented in the instruction as the PC value plus or minus a numeric

offset. The assembler calculates the required offset from the label and the address of the

current instruction. If the offset is too big, the assembler produces an error.

•

For the B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the

current instruction plus four bytes.

•

For all other instructions that use labels, the value of the PC is the address of the

current instruction plus four bytes, with bit[1] of the result cleared to 0 to make it word-

aligned.

•

Your assembler might permit other syntaxes for PC-relative expressions, such as a

label plus or minus a number, or an expression of the form [PC, #number].

3.3.7

Conditional execution

Most data processing instructions can optionally update the condition flags in the application

program status register (APSR) according to the result of the operation (see Application

program status register on page 20). Some instructions update all flags, and some only

update a subset. If a flag is not updated, the original value is preserved. See the instruction

descriptions for the flags they affect.

You can execute an instruction conditionally, based on the condition flags set in another

instruction:

•

Immediately after the instruction that updated the flags

•

After any number of intervening instructions that have not updated the flags

PM0214 Arkusz danych(PDF) 64 Page - STMicroelectronics

PM0214 Arkusz danych(HTML) 64 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL