LTC1410CSW datasheet(6/16 Pages) LINER

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LTC1410

PI FU CTIO S

+AIN (Pin 1): Positive Analog Input, ±2.5V.

–AIN (Pin 2): Negative Analog Input, ±2.5V.

VREF (Pin 3): 2.50V Reference Output.

REFCOMP (Pin 4): 4.06V Reference Bypass Pin. By-

pass to AGND with 10

µF tantalum in parallel with 0.1µF

ceramic.

AGND (Pin 5): Analog Ground.

D11 to D4 (Pins 6 to 13): Three-State Data Outputs.

DGND (Pin 14): Digital Ground for Internal Logic. Tie to

AGND.

D3 to D0 (Pins 15 to 18): Three-State Data Outputs.

OGND (Pin 19): Digital Ground for Output Drivers. Tie

to AGND.

NAP/SLP (Pin 20): Power Shutdown Mode. Selects the

mode invoked by the SHDN pin. Low selects Sleep

mode and high selects quick wake-up Nap mode.

FU CTIO AL BLOCK DIAGRA

12-BIT CAPACITIVE DAC

COMP

REF AMP

2.5V REF

REFCOMP

(4V)

CSAMPLE

•

D11

BUSY

CONTROL LOGIC

CONVST RD

SHDN

INTERNAL

CLOCK

NAP/SLP

ZEROING SWITCHES

DVDD

VSS

AVDD

+AIN

–AIN

VREF

AGND

DGND

LTC1410 • BD

–

SUCCESSIVE APPROXIMATION

OUTPUT LATCHES

SHDN (Pin 21): Power Shutdown Input. A low logic

level will invoke the Shutdown mode selected by the

NAP/SLP pin.

RD (Pin 22): Read Input. This enables the output

drivers when CS is low.

CONVST (Pin 23): Conversion Start Signal. This active

low signal starts a conversion on its falling edge.

CS (Pin 24): The Chip Select input must be low for the

ADC to recognize CONVST and RD inputs.

BUSY (Pin 25): The BUSY output shows the converter

status. It is low when a conversion is in progress. Data

valid on the rising edge of BUSY.

VSS (Pin 26): –5V Negative Supply. Bypass to AGND

with 10

µF tantalum in parallel 0.1µF ceramic.

DVDD (Pin 27): 5V Positive Supply. Short to Pin 28.

AVDD (Pin 28): 5V Positive Supply. Bypass to AGND

with 10

µF tantalum in parallel with 0.1µF ceramic.

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