LTC1410CSW datasheet(7/16 Pages) LINER

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LTC1410

TEST CIRCUITS

APPLICATIONS INFORMATION

CONVERSION DETAILS

The LTC1410 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 12-bit

capacitive DAC output is sequenced by the SAR from the

Most Significant Bit (MSB) to the Least Significant Bit

(LSB). Referring to Figure 1, the + AIN and – AIN inputs are

connected to the sample-and-hold capacitors (CSAMPLE)

during the acquire phase and the comparator offset is

nulled by the zeroing switches. In this acquire phase, a

minimum duration of 100ns will provide enough time for

the sample-and-hold capacitors to acquire the analog

signal. During the convert phase the comparator zeroing

switches open, putting the comparator into compare

mode. The input switches connect the CSAMPLE capacitors

to ground, transferring the differential analog input charge

DBN

(A) Hi-Z TO VOH AND VOL TO VOH

(B) Hi-Z TO VOL AND VOH TO VOL

DBN

1410 TC01

100pF

DBN

(A) VOH TO Hi-Z

(B) VOL TO Hi-Z

DBN

1410 TC02

Load Circuits for Access Timing

Load Circuits for Output Float Delay

onto the summing junctions. This input charge is succes-

sively compared with the binarily-weighted charges sup-

plied by the differential capacitive DAC. Bit decisions are

made by the high speed comparator. At the end of a

conversion, the differential DAC output balances the + AIN

and – AIN input charges. The SAR contents (a 12-bit data

word) which represent the difference of + AIN and – AIN are

loaded into the 12-bit output latches.

SAMPLE

HOLD

+CSAMPLE

–CSAMPLE

•

D11

ZEROING SWITCHES

+AIN

+CDAC

+VDAC

–CDAC

–VDAC

–AIN

1410 F01

COMP

–

OUTPUT

LATCHES

SAR

SAMPLE

HOLD

Figure 1. Simplified Block Diagram

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