5

LTC1642

APPLICATIO S I FOR ATIO

Hot Circuit Insertion

When a circuit board is inserted into a live backplane its

supply bypass capacitors can draw large currents from the

backplane power bus as they charge. These currents can

permanently damage connector pins and can glitch the

backplane supply, resetting other boards in the system.

The LTC1642 limits the charging currents drawn by a

board’s capacitors, allowing safe insertion in a live

backplane.

Power Supply Ramping

In the circuit shown in Figure 1 the LTC1642 and the

external N-channel pass transistor Q1 work together to

the chip holds Q1’s gate at ground. After a programmable

delay a 25

µA current source begins to charge the external

capacitor C2, generating a voltage ramp of 25

µA/C2 V/s at

the GATE pin. Because Q1 acts as a source follower while

its gate ramps, the current charging the board’s bypass

An internal charge pump supplies the 25

µA gate current,

from the GATE pin to ground. Resistor R3 limits this

Zener’s transient current during board insertion and re-

moval and protects against high frequency FET oscilla-

tions.

The delay before the GATE pin voltage begins ramping is

determined by the system timer. It comprises an external

capacitor C1 from the RST TMR pin to ground; an internal

2

comparator, with the positive input tied to RST TMR and

the negative input tied to the 1.23V reference; and an

NMOS pull-down. In standby, the NMOS holds RST TMR

at ground; when the timer starts the NMOS turns off and

the RST TMR voltage ramps up as the current source

charges the capacitor. When RST TMR reaches 1.23V the

timer comparator trips; the GATE voltage begins ramping

and RST TMR returns to ground. The ramp time

∆t needed

to trip the comparator is :

∆t(ms) = 615•C1(µF).

GATE

ON

14

SENSE

15

RESET

5

4

BRK TMR

2

16

R2

0.010

Ω

Q1

FDR9410A

GND

LTC1642

8

RST TMR

3

1642 F01

R3

100

Ω

R4

330

Ω

C2

0.047

µF

+

C7

0.1

µF

C1

0.33

µF

C4

0.33

µF

ALL RESISTORS

±5% UNLESS NOTED

RESET DELAY = 200ms

SHORT-CIRCUIT DURATION = 20ms

12V

2.5A

R1

10k

Figure 1. Supply Control Circuitry

Figure 2. Supply Control Timing

1642 F02

TIME

GATE

SLOPE = 25

µA/C(V/s)

RST TMR

Powering-Up In Current Limit

Ramping the GATE pin voltage

indirectly limits the charg-

ing current to I = 25

worst-case design can often result in needlessly long

ramp times, and it may be better to limit the charging

current directly.

Current Limiting and Solid-State Circuit Breaker

The board current can be limited by connecting a sense

internal servo loop adjusts the GATE pin voltage such that

Q1 acts as a constant current source if the voltage drop

across the sense resistor reaches a limit. The voltage limit

across the sense resistor increases as the output charges