LTC1647-3IGN datasheet(11/20 Pages) LINER

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LTC1647-1/LTC1647-2/LTC1647-3

Power Supply Ramping

VOUT is controlled by placing MOSFET Q1 in the power

path (Figure 1). R1 provides load current fault detection

and R2 prevents MOSFET high frequency oscillation. By

ramping the gate of the pass transistor at a controlled rate

(dV/dt = 10

µA/C1), the transient surge current

(I = CLOAD•dV/dt = 10µA•CLOAD/C1) drawn from the main

backplane is limited to a safe value when the board is

inserted into the connector.

When power is first applied to VCC, the GATE pin pulls low.

A low-to-high transition at the ON pin initiates GATE ramp-

up. The rising dV/dt of GATE is set by 10

µA/C1 (Figure 5),

where C1 is the total external capacitance between GATE

and GND. The ramp-up time for VOUT is equal to

t = (VCC•C1)/10µA.

A high-to-low transition at the ON pin initiates a GATE

ramp-down at a slope of – 50

µA/C1. This rate is usually

adequate as the supply bypass capacitors take time to

discharge through the load.

If the ON pin is connected to VCC, or is pulled high before

VCC is first applied, GATE is held low until VCC rises above

the undervoltage lockout threshold, VLKO (Figure 6). Once

the threshold is exceeded, GATE ramps at a controlled rate

of 10

µA/C1. When the power supply is disconnected, the

body diode of Q1 holds VCC about 700mV below VOUT. The

GATE voltage droops at a rate determined by VCC. If VCC

drops below VLKO – VLKH, the LTC1647 enters UVLO and

GATE pulls down to GND.

Autoretry

The LTC1647-2 and LTC1647-3 are designed to allow an

automatic reset of the electronic circuit breaker after a

fault condition occurs. This is accomplished by pulling the

ON/FAULT (LTC1647-2) pin or the ON and FAULT pins tied

together (LTC1647-3) high through a resistor, R3, as

shown in Figure 7. An autoretry sequence begins if a fault

occurs. If the circuit breaker trips, FAULT pulls the ON pin

low. After a tRESET interval elapses, FAULT resets and R3

Figure 5. Supply Turn-On/Off with ON

Figure 7. Autoretry Sequence

APPLICATIO S I FOR ATIO

VCC + ∆VGATE

VCC

VON

CLOAD DISCHARGES

RAMP-DOWN

SLOPE = –50

µA/C1

RAMP-UP

SLOPE = 10

µA/C1

VOUT

VGATE

1647-1/2/3 F05

VCC + ∆VGATE

VCC

VLKO

VLKO – VLKH

CLOAD DISCHARGES

VCC

UNPLUGGED

OUT OF UVLO

INTO UVLO

FAST RAMP-DOWN

AT UNDERVOLTAGE

LOCKOUT

VGATE DROOP

DUE TO VCC

RAMP-UP

SLOPE = 10

µA/C1

VOUT

VGATE

1647-1/2/3 F06

SENSE

ON/FAULT

VCC

VOUT

FAULT

(5V LOGIC)

GND

GATE

LTC1647-2

10nF

Ω

0.01

Ω

IRF7413

CLOAD

VCC

15k

0.1

µF

tRESET

tDELAY

tRAMP

VCC – VSENSE

VGATE

VFAULT

1647-1/2/3 F07

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