TAS2553_15 datasheet(48/58 Pages) TI

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TAS2553

SLAS978B – SEPTEMBER 2013 – REVISED FEBRUARY 2014

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10 Layout

10.1 Layout Guidelines

•

Place the boost inductor between VBAT and SW close to device terminals with no VIAS between the device

terminals and the inductor.

•

Place the capacitor between VREG and VBOOST close to device terminals with no VIAS between the device

terminals and capacitor.

•

Place the capacitor between VBOOST/PVDD and GND close to device terminals with no VIAS between the

device terminals and capacitor.

•

Do not use VIAS for traces that carry high current. These include the traces for VBOOST, SW, PVDD and the

speaker OUT+, OUT-.

•

Use epoxy filled vias for the interior pads.

•

Connect VSENSE+, VSENSE- as close as possible to the speaker.

–

VSENSE+, VSENSE- should be connected between the EMI ferrite and the speaker if EMI ferrites are

used on OUT+, OUT-.

–

VSENSE+, VSENSE- should be connected between the EMI ferrite and the EMI capacitor if EMI

capacitors are used. EMI ferrites must be used if EMI capacitors are used on OUT+, OUT-.

•

If the analog inputs, IN+ and IN-, are:

–

used, analog input traces should be routed symmetrically for true differential performance.

–

used, do not run analog input traces parallel to digital lines.

–

used, they should be ac coupled.

–

not used, they should be shorted together.

•

Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for

minimum ground noise.

•

Use supply decoupling capacitors as shown in Figure 51 and Figure 56 and described in Power Supply

Recommendations.

•

Place EMI ferrites, if used, close to the device.

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