DLPC910 datasheet(21/50 Pages) TI1

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DLPC910

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DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

7.3.6.5.2

Load4 Block Clears

While Load4 is enabled, Block Clear requests will be ignored. To load using Load4 followed by Block Clear

request(s), simply de-assert LOAD4_ENZ at the beginning of the MCP request(s) preceding the Block Clear

request(s). Re-assert LOAD4_ENZ at the beginning of the MCP request(s) preceding the next desired Load4

operation. This will ensure that the DLPC910 controller has sufficient time to disable or enable LOAD4_ENZ

before data is loaded or Block Clear(s) are requested. Refer to Block Clear regarding block clear operation.

7.3.7 Status Interface

7.3.7.1 ECP2 Finished

When power is applied, the ECP2_FINISHED signal goes high to indicate the DLPC910 has completed loading

the configuration from the DLPR910 prom.

7.3.7.2 Initialization Active

The initialization active signal INIT_ACTIVE indicates that the DMD and the DLPC910 digital controller are in an

initialization state after power is applied. During this initialization period, the DLPC910 is calibrating the data

interface, and initializing the DMD by setting all internal registers to their correct states. Monitoring the

INIT_ACTIVE signal should not begin until ECP2_FINISHED goes high. When this signal goes low, the system

has completed initialization. System initialization takes approximately 4 ms to complete. Data and command write

cycles must not be asserted during the initialization. This signal is driven by a CLK_R register and should be

considered an asynchronous signal. Standard synchronization techniques should be applied if monitoring this

signal with a synchronous circuit clocked by a clock other than CLK_R. After initialization is complete, a delay of

at least 64 clocks should be observed before the first DVALID is asserted (to ensure a clean start up process).

NOTE

The RST2BLKZ, COMP_DATA, and NS_FLIP signals should be kept low during

initialization to ensure proper setup of the system.

7.3.7.3 Reset Active

The reset active signal RST_ACTIVE goes high for approximately 4 µs, indicating a MCP operation is in

progress. During this time, no additional MCPs will be accepted by the DLPC910 until RST_ACTIVE returns low.

RST_ACTIVE does not return to low unless continuous no-op or data loading row cycles are issued.

After PWR_FLOAT is asserted, a Mirror Clocking Pulse is issued, or a mirror Float operation is requested,

RST_ACTIVE is asserted to indicate that the operation is in progress. Each RST_ACTIVE pulse applies to one or

more MCPs depending on the reset block operation chosen from Table 5. RST_ACTIVE is synchronized to an

internal version of DDC_DCLK. As such, circuits in the application FPGA should consider this signal

asynchronous and use standard synchronization techniques to assure reliable registering of this signal.

7.3.7.4 DMD_IRQ

The DMD_IRQ signal indicates a DMD power fault of one of the bias, offset, or reset power supplies. If the

customer interface wishes to monitor this signal, it must first be enabled in the DESTOP_INTERRUPT Register.

The cause of the fault should be determined and resolved prior to a system reset to continue operation. The

customer interface can also monitor this event by polling the DESTOP_INTERRUPT Register via the I2C

interface.

7.3.7.5 LED Indicators

7.3.7.5.1

VLED0

The VLED0 signal is typically connected to an LED to show that the DLPC910 is operating normally. The signal

is 1 Hz with 50% duty cycle, otherwise known as the heartbeat.

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