DLPC910 datasheet(39/50 Pages) TI1

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DLPC910

DLPR910

DLP9000X

12 V

3.3 V

2.5 V

1.8 V

1.0 V

3.45 V

VCCO

VCC_AUX

VCCINT

VCC

Power Management

VCC0

DLPC910

www.ti.com

DLPS064A – SEPTEMBER 2015 – REVISED OCTOBER 2015

9 Power Supply Recommendations

9.1 Power Supply Distribution and Requirements

The DLPC910ZYR, the DLPR910YVA, and the DLP9000XFLS DMD are powered by a power distribution as

shown in Figure 16.

Figure 16. Power Distribution

9.2 Power Down Sequence

Prior to power removal, the Apps FPGA should assert PWR_FLOAT and allow approximately 300

μs for the

procedure to complete. This procedure will assure the mirrors are in a flat state. Following this procedure, the

power can be safely removed. To restart after assertion of PWR_FLOAT, the DLPC910 must be reset

(CTRL_RSTZ low then high) or power must be cycled.

10 Layout

10.1 Layout Guidelines

One of the most important factors to gain good performance is designing the PCB with the highest quality signal

integrity possible. The following PCB design guidelines provide a reference of an interconnect system..

10.1.1 PCB Design Standards

PCBs should be designed and built in accordance with the industry specifications shown in Table 19.

Table 19. Industry Design Specifications

INDUSTRY SPECIFICATION

APPLICABLE TO

IPC-2221 and IPC2222, Type 3, Class X, at Level B producibility

Board design

IPC-6011 and IPC-6012, Class 2

PWB fabrication

IPC-SM-840, Class 3, Color Green

Finished PWB solder mask

UL94V-0 Flammability Rating and Marking

Finished PWB

UL796 Rating and Marking

Finished PWB

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