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AD6679 Arkusz danych(PDF) 64 Page - Analog Devices

Numer części AD6679
Szczegółowy opis  135 MHz BW IF Diversity Receiver
PDF  81 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD6679 Arkusz danych(HTML) 64 Page - Analog Devices

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AD6679
Data Sheet
Rev. B | Page 64 of 81
MULTICHIP SYNCHRONIZATION
The AD6679 has a SYNC± input that allows the user flexible
options for synchronizing the internal blocks. The SYNC±
input is a source synchronous system reference signal that
enables multichip synchronization. The input clock divider,
DDCs, and signal monitor block can be synchronized using the
SYNC± input. For the highest level of timing accuracy, SYNC±
must meet the setup and hold requirements relative to the
CLK± input.
The flowchart in Figure 84 shows the internal mechanism by
which multichip synchronization can be achieved in the AD6679.
The AD6679 supports several features that aid users in meeting
the requirements for capturing a SYNC± signal. The SYNC±
sample event is defined as either a synchronous low to high
transition or a synchronous high to low transition. Additionally,
the AD6679 allows the SYNC± signal to be sampled using
either the rising edge or falling edge of the CLK± input. The
AD6679 also can ignore a programmable number (up to 16) of
SYNC± events. The SYNC± control options can be selected using
Register 0x120 and Register 0x121.
YES
UPDATE
SETUP/HOLD
DETECTOR STATUS
(REG 0x128)
INCREMENT
SYNC± IGNORE
COUNTER
YES
NO
SYNC±
ENABLED?
(REG 0x120)
NO
CLOCK
DIVIDER
> 1?
(REG 0x10B)
YES
NO
INPUT
CLOCK
DIVIDER
ALIGNMENT
REQUIRED?
YES
NO
NO
YES
ALIGN CLOCK
DIVIDER
PHASE TO
SYNC
DDC NCO
ALIGNMENT
ENABLED?
(REG 0x300)
NO
RESET
SYNC± IGNORE
COUNTER
NO
START
SYNC±
ASSERTED?
YES
NO
YES
ALIGN SIGNAL
MONITOR
COUNTERS
YES
NO
NO
INCREMENT
SYNC±
COUNTER
(REG 0x12A)
BACK TO START
SYNC±
IGNORE
COUNTER
EXPIRED?
(REG 0x121)
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
(REG 0x10D)
SIGNAL
MONITOR
SYNC
ENABLED?
(REG 0x26F)
ALIGN PHASE OF ALL
INTERNAL CLOCKS
TO SYNC±
YES
CLOCK
ALIGNMENT
REQUIRED?
ALIGN DDC
NCO PHASE
ACCUMULATOR
Figure 84. Multichip Synchronization



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