AD6679 datasheet(69/81 Pages) AD

69 / 81 page

Data Sheet

AD6679

Rev. B | Page 69 of 81

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into seven sections: the

Analog Devices, Inc., SPI registers, the analog input buffer

control registers, ADC function registers, the DDC function

registers, NSR decimate by 2 and noise shaping requantizer

registers, variable dynamic range registers, and the digital

outputs and test modes registers.

Table 41 (see the Memory Map Register Table section)

documents the default hexadecimal value for each hexadecimal

address shown. The column with the heading Bit 7 (MSB) is the

start of the default hexadecimal value given. For example,

Address 0x561, the output format register, has a hexadecimal

default value of 0x01. This means that Bit 0 = 1, and the

remaining bits are 0s. This setting is the default output format

value, which is twos complement. For more information on this

function and others, see Table 41.

Open and Reserved Locations

All address and bit locations that are not included in Table 41

are not currently supported for this device. Write unused bits of

a valid address location with 0s unless the default value is set

otherwise. Writing to these locations is required only when part

of an address location is open (for example, Address 0x561). If

the entire address location is open (for example, Address 0x013),

do not write to this address location.

Default Values

After the AD6679 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 41.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

•

“X” denotes “don’t care”.

Channel Specific Registers

Some channel setup functions such as analog input differential

termination (Register 0x016) can be programmed to a different

value for each channel. In these cases, channel address locations

are internally duplicated for each channel. These registers and bits

are designated in Table 41 as local. These local registers and bits

can be accessed by setting the appropriate Channel A or

Channel B bits in Register 0x008. If both bits are set, the

subsequent write affects the registers of both channels. In a read

cycle, set only Channel A or Channel B to read one of the two

registers. If both bits are set during an SPI read cycle, the device

returns the value for Channel A. Registers and bits designated as

global in Table 41 affect the entire device and the channel features

for which independent settings are not allowed between

channels. The settings in Register 0x008 do not affect the global

registers and bits.

SPI Soft Reset

After issuing a soft reset by programming 0x81 to Register 0x000,

the AD6679 requires 5 ms to recover. Therefore, when program-

ming the AD6679 for application setup, ensure that an adequate

delay is programmed into the firmware after asserting the soft

reset and before starting the device setup.

Datapath Soft Reset

After programming the desired clock divider settings, changing

the input clock frequency, or glitching the input clock, a datapath

soft reset is recommended by writing 0x02 to Register 0x001.

This reset function restarts all the datapath and clock generation

circuitry in the device. The reset occurs on the first clock cycle

after the register is programmed and the device requires 5 ms to

recover. This reset does not affect the contents of the memory

map registers.

AD6679 Arkusz danych(PDF) 69 Page - Analog Devices

AD6679 Arkusz danych(HTML) 69 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Arkusz danych Pobierz

Link URL