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FDC2114QRGHTQ1 Arkusz danych(PDF) 6 Page - Texas Instruments

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Numer części FDC2114QRGHTQ1
Szczegółowy opis  Capacitance-to-Digital Converter (FDC) for Capacitive Sensing
PDF  58 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

FDC2114QRGHTQ1 Arkusz danych(HTML) 6 Page - Texas Instruments

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FDC2112-Q1, FDC2114-Q1, FDC2212-Q1, FDC2214-Q1
SNOSCZ9 – MAY 2016
www.ti.com
Product Folder Links: FDC2112-Q1 FDC2114-Q1 FDC2212-Q1 FDC2214-Q1
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Copyright © 2016, Texas Instruments Incorporated
Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA = 25°C, VDD = 3.3 V
(1)
PARAMETER
TEST CONDITIONS(2)
MIN(3)
TYP(4)
MAX(3)
UNIT
MASTER CLOCK
fCLKIN
External master clock input
frequency (CLKIN)
TA = –40°C to 125°C
2
40
MHz
CLKINDUTY_MIN
External master clock
minimum acceptable duty
cycle (CLKIN)
40%
CLKINDUTY_MAX
External master clock
maximum acceptable duty
cycle (CLKIN)
60%
VCLKIN_LO
CLKIN low voltage threshold
0.3 VDD
V
VCLKIN_HI
CLKIN high voltage threshold
0.7 × VDD
V
fINTCLK
Internal master clock
frequency range
35
43.4
55
MHz
TCf_int_μ
Internal master clock
temperature coefficient mean
–13
ppm/°C
(1)
This parameter is specified by design and/or characterization and is not tested in production.
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
tSDWAKEUP
Wake-up time from SD high-low transition to I2C readback
2
ms
tSLEEPWAKEUP Wake-up time from sleep mode
0.05
ms
tWD-TIMEOUT
Sensor recovery time (after watchdog timeout)
5.2
ms
I2C TIMING CHARACTERISTICS
fSCL
Clock frequency
10
400
kHz
tLOW
Clock low time
1.3
μs
tHIGH
Clock high time
0.6
μs
tHD;STA
Hold time (repeated) START condition: after this period, the first clock
pulse is generated
0.6
μs
tSU;STA
Setup time for a repeated START condition
0.6
μs
tHD;DAT
Data hold time
0
μs
tSU;DAT
Data setup time
100
ns
tSU;STO
Setup time for STOP condition
0.6
μs
tBUF
Bus free time between a STOP and START condition
1.3
μs
tVD;DAT
Data valid time
0.9
μs
tVD;ACK
Data valid acknowledge time
0.9
μs
tSP
Pulse width of spikes that must be suppressed by the input filter(1)
50
ns



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