TUSB3410 datasheet(85/92 Pages) TI

85 / 92 page

11–15

11.9.1.2 Interrupt Handling Routine

The higher-vector number has a higher priority than the lower-vector number. Table 11–11 lists all the interrupts and

source of interrupts.

Table 11–11. Vector Interrupt Values and Sources

G[3:0]

(Hex)

I[2:0]

(Hex)

VECTOR

(Hex)

INTERRUPT SOURCE

INTERRUPT SOURCE SHOULD BE

CLEARED

No Interrupt

No Source

Output–endpoint–1

VECINT register

Output–endpoint–2

VECINT register

Output–endpoint–3

VECINT register

Output–endpoint–4

VECINT register

4–7

→1E

NOT USED

Input–endpoint–1

VECINT register

Input–endpoint–2

VECINT register

Input–endpoint–3

VECINT register

Input–endpoint–4

VECINT register

4–7

→2E

NOT USED

STPOW packet received

USBSTA/ VECINT registers

SETUP packet received

USBSTA/ VECINT registers

PSOF interrupt

USBSTA/ VECINT registers

RESR interrupt

USBSTA/ VECINT registers

FSPR interrupt

USBSTA/ VECINT registers

RTSR interrupt

USBSTA/ VECINT registers

HSTL interrupt

USBSTA/ VECINT registers

NOT USED

I2C TXE interrupt

VECINT register

I2C TXE interrupt

VECINT register

Input–endpoint–0

VECINT register

Output–endpoint–0

VECINT register

4–7

→4E

NOT USED

UART1 status interrupt

LSR/VECNT register

UART1 modern interrupt

LSR/VECINT register

3–7

→5E

NOT USED

UART1 RXF interrupt

LSR/VECNT register

UART1 TXE interrupt

LSR/VECINT register

2–7

→6E

NOT USED

0–7

→7E

NOT USED

DMA1 interrupt

DMACSR/VECNT register

NOT USED

DMA3 interrupt

DMACSR/VECNT register

3–7

→7E

NOT USED

9–15

0–7

→FE

NOT USED

TUSB3410 Arkusz danych(PDF) 85 Page - Texas Instruments

TUSB3410 Arkusz danych(HTML) 85 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Arkusz danych Pobierz

Link URL