TUSB3410 datasheet(23/92 Pages) TI

23 / 92 page

4–3

Once the code is loaded, the MCU sets SDW = 1. This switches the memory map to normal mode; i.e. the 16K RAM

is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets

CONT = 1 (in the USBCTL register). This connects the device to the USB and results in normal USB device

enumeration.

4.1.3

WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93)

A watchdog timer (WDT) with 1-ms clock is provided. If this register is not accessed for a period of 128 ms, the WDT

counter resets the MCU. (see Figure 5–1). The watchdog timer is enabled by default and can be disabled by writing

a pattern of 101010 into the WDD[5:0] bits.

765

ROA

SDW

R/W

W/O

BIT

NAME

RESET

FUNCTION

WDT

MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1

in a period of 128 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (WDT is a

7-bit counter using a 1-ms CLK). This bit is read as 0.

5–1

WDD[5:1]

00000

These bits are used to disable the watchdog timer. For the timer to be disabled these bits must be set

to 10101 and WDD[0] must also be set to 0. If any other pattern is present, the watchdog timer is in

operation.

WDR

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or

watchdog timer reset.

WDR = 0

A power-up reset occurred

WDR = 1

A USB reset or watchdog time-out reset occurred. To clear this bit, the MCU must write a 1.

Writing a 0 has no effect.

WDD[0]

This bit is one of the disable bits for the watchdog timer. This bit must be cleared in order for the

watchdog timer to be disabled.

4.2

Buffers + I/O RAM Map

The address range from F800 to FFFF (2K bytes) is reserved for data buffers, setup packet, endpoint descriptors

block (EDB), and all I/O. There are 128 locations reserved for MMR (memory mapped registers). Table 4–2

represents the XDATA space allocation and access restriction for the DMA, UBM, and MCU.

Table 4–2. XDATA Space

DESCRIPTION

ADDRESS RANGE

UBM ACCESS

DMA ACCESS

MCU ACCESS

Internal MMRs

(Memory Mapped Registers)

FFFF

↑

FF80

(Only EDB-0)

(only Data reg. and EDB-0)

Yes

EDB

(Endpoint Descriptors Block)

FF7F

↑

FF08

Only for EDB update

Yes

Setup Packet

FF07

↑

FF00

Yes

Input Endpoint-0 Buffer

FEFF

↑

FEF8

Yes

Output Endpoint-0 Buffer

FEF7

↑

FEF0

Yes

Data Buffers

FEEF

↑

F800

Yes

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