REV. B

AD1981B

–25–

SPLNK

SPDIF Link. This bit enables the SPDIF to link with the DAC for data requesting.

0 = SPDIF and DAC are not linked.

1 = SPDIF and DAC are linked and receive the same data requests (reset default).

SPDZ

SPDIF DACZ.

0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).

1 = Forces midscale sample out the SPDIF stream if FIFO underruns.

SPAL

SPDIF ADC Loop-Around.

0 = SPDIF transmitter is connected to the ac-link stream (reset default).

1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.

INTS

Interrupt Mode Select. This bit selects the JS interrupt implementation path.

0 = Bit 0 SLOT 12 (modem interrupt).

1 = Slot 6 valid bit (MIC ADC interrupt).

CHEN

Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).

0 = Disable chaining (reset default).

1 = Enable chaining into ID0 pin.

REGM0

Master Codec Register Mask.

REGM1

Slave 1 Codec Register Mask.

REGM2

Slave 2 Codec Register Mask.

SLOT16

Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a

preferred mode for DSP serial port interfacing.

MBG[1:0]

MIC Boost Gain Change Register.

These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.

Note: This gain setting takes affect only while Bit D6 (M20) on the MIC volume register (0Eh) is set to 1; otherwise,

the MIC boost block has a gain of 0 dB.

00 = 20 dB gain (reset default).

01 = 10 dB gain.

10 = 30 dB gain.

11 = Reserved.

VREFD

selection (see below).

VREFH

Miscellaneous Control Bit Register (Index 76h)

Reg

No. Name

D15

D14 D13

D12

D11

D10 D9

D8 D7

D6

D5 D4

D3

D2

D1

D0

Default

76th Misc

DACZ

X

MSPLT LODIS DAM

X

FMXE X

MADPD 2CMIC X

MADST VREFH VREFD MBG1 MBG0 0000h

Control Bits

All registers not shown and bits containing an X are assumed to be reserved.

Serial Configuration Register (Index 74h)

Reg

No. Name D15

D14

D13

D12

D11 D10 D9 D8

D7 D6 D5 D4

D3 D2

D1

D0

Default

74h Serial

SLOT16 REGM2 REGM1 REGM0 X

X

X

CHEN XXX

INTS X

SPAL SPDZ SPLNK 7001h

Configuration

This register is not reset when the reset register (Register 00h) is written. All registers not shown and bits containing an X are assumed to be reserved.