DP83256 datasheet(6/146 Pages) TI1

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20 Architecture Description

21 BLOCK OVERVIEW

The PLAYERa device is comprised of six blocks Clock

Recovery Receiver Configuration Switch Transmitter Sta-

tion Management (SMT) Support and Clock Generation

Module as shown in

Figure 2-1

Clock Recovery

The Clock Recovery Module accepts a 125 Mbps NRZI data

stream from the external PMD receiver It then provides the

extracted and synchronized data and clock to the Receiver

block

The Clock Recovery Module performs the following opera-

tions

Locks to and tracks the incoming NRZI data stream

Extracts data stream and synchronized 125 MHz clock

Receiver

During normal operation the Receiver Block accepts serial

data as inputs at the rate of 125 Mbps from the Clock Re-

covery Module During the Internal Loopback mode of oper-

ation the Receiver Block accepts data directly from the

Transmitter Block

The Receiver Block performs the following operations

Optionally converts the incoming data stream from NRZI

to NRZ

Decodes the data from 5B to 4B coding

Converts the serial bit stream into 10-bit bytes composed

of 8 bits data 1 bit parity and 1 bit control information

Compensates for the differences between the upstream

station clock and the local clocks

Decodes Line States

Detects link errors

Presents data symbol pairs (bytes) to the Configuration

Switch Block

Configuration Switch

An FDDI station may be in one of three configurations Iso-

late Wrap or Thru The Configuration Switch supports these

configurations by switching the transmitted and received

data paths between PLAYERa devices and one or more

MACSI devices

The configuration switch is integrated into the PLAYERa

device therefore no external logic is required for this func-

tion

Setting the Configuration switch can be done explicitly via

the Control Bus Interface or it can be set automatically with

the CF

React SMT Support feature

TLF11708 – 2

FIGURE 2-1 PLAYERa Device Block Diagram

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